Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Some memory systems scramble, or randomize, the data before storing it in memory. For example, U.S. Patent Application Publication 2008/0215798, whose disclosure is incorporated herein by reference, describes randomization schemes, in which original data to be stored in a non-volatile memory are first randomized while preserving the size of the original data. In response for a request for the original data, the randomized data are retrieved, de-randomized and exported without authenticating the requesting entity. ECC encoding is applied either before or after randomizing. Correspondingly, ECC decoding is applied either after or before de-randomizing.
U.S. Patent Application Publication 2009/0204824, whose disclosure is incorporated herein by reference, describes data scrambling techniques implemented externally to a Flash memory device. The data scrambling technique preferably uses a logical address, such as logical block address or logical page address, rather than a physical address, to determine a seed scrambling key.
PCT International Publication WO 2008/099958, whose disclosure is incorporated herein by reference, describes a method of writing data into a semiconductor memory, in which nonvolatile memory cells each having a gate connected to a word line are connected in series. A scrambling method for the data is selected according to a word line address of the memory cells into which the data is to be written. The data is scrambled using the selected scrambling method, and the scrambled data is written into the memory cells according to the word line address.
U.S. Pat. No. 4,993,029, whose disclosure is incorporated herein by reference, describes a method and apparatus for randomizing data in a direct access storage device. The data is randomized, and subsequently de-randomized, in a repeating or pseudo-random, complementary sequence for each byte. The complementary randomizing/de-randomizing sequence is determined by the count contained in a counter. This counter is initialized at the beginning of a record, and is progressively incremented to the predetermined next count as each byte is processed.